1. Field of the Invention
The present invention relates to a solid-state imaging apparatus including a reset-level supply circuit for supplying a predetermined reset level to photoelectric conversion pixels.
2. Description of the Related Art
Referring to the circuit diagram illustrating a conventional signal-amplifying solid-state imaging apparatus shown in FIG. 1, a pixel 1 is formed of a photodiode 2 for converting a light signal into an electric charge; an amplifying MOS transistor 3 for storing the light signal charge, converting the voltage of the charge and outputting it; a selection MOS transistor 4 which serves as a selection switch for the pixel 1; and a resetting MOS transistor 5 for resetting the photodiode 2 and the amplifying MOS transistor 3.
Devices for resetting the pixel 1 include a resetting MOS transistor 8 for resetting the pixel 1, a terminal 13 for supplying a reset pulse to the resetting MOS transistor 8, a reset voltage terminal 9 for temporarily supplying a reset voltage to the pixel 1, a terminal 18 for inputting a switch pulse into the resetting MOS transistor 5 of the pixel 1, and a line-selecting MOS transistor 19 for selecting the line to which the pulse output from the terminal 18 is applied according to the output of a vertical shift register 24.
Devices for storing an output voltage of the pixel 1 include a capacitor 10 for temporarily storing the output voltage of the pixel 1, a MOS transistor 11 for reading and writing the charge of a vertical output line 6 from and into the capacitor 10, a terminal 14 for supplying a write/read pulse to the MOS transistor 11, a current-load MOS transistor 7 that forms, together with the amplifying MOS transistor 3, an inversion amplifier, a terminal 15 for supplying a load pulse to the MOS transistor 7, a power supply terminal 12 for supplying a supply voltage to the MOS transistors 3 and 7, a terminal 16 for supplying a transfer pulse to the selection MOS transistor 4, and a buffer MOS transistor 17 for buffering the pulse output from the terminal 16.
Devices for reading an output voltage from the pixel 1 include the vertical output line 6 for outputting a pixel signal, a horizontal output line 20 for outputting an output voltage of the individual pixels 1, a transfer MOS transistor 21 for transferring the stored voltage of the capacitor 10 to the horizontal output line 20 according to an output of a horizontal shift register 25, a preamplifier 22 for amplifying the horizontal output line 20 and outputting it, an output terminal 23 of the preamplifier 22, vertical shift register lines 26 and 26xe2x80x2 of the vertical shift register 24, and horizontal shift register lines 27 and 27xe2x80x2 of the horizontal shift register 25.
For simple representation, a 2xc3x972-pixel matrix is shown in FIG. 1. Although the MOS transistor shown in FIG. 1 is an N-type MOS transistor, it may be formed by a P-type MOS transistor, in which case, the polarity of the driving pulse may be inverted, and the power supply and the ground may also be inverted.
FIG. 2 is a timing chart of drive pulses for the circuit shown in FIG. 1. The operation of a conventional solid-state imaging apparatus is described below with reference to FIG. 2.
In the solid-state imaging apparatus, the pixels 1 are first reset by an output of the vertical shift register 24 via the vertical shift register lines 26. This resetting operation is performed by sequentially resetting the individual lines, i.e., the first line, the second line, and so on, of the output lines 26.
More specifically, the resetting operation is performed as follows. The terminals 13 and 18 are first caused to be at a high level, and the resetting MOS transistors 5 and 8 corresponding to the line selected by the line-selecting MOS transistor 19 are switched on, thereby resetting the cathodes of the photodiodes 2 and the gates of the amplifying MOS transistors 3 having light-signal electric charges. Accordingly, when the voltage supplied from the reset voltage terminal 9 is indicated by VRS, the reset voltage to be applied to the pixels 1 is also indicated by VRS.
Subsequently, the terminals 14, 15, and 16 are caused to be at a high level, and the MOS transistors 11, 7, and 4 corresponding to the line selected by the line-selecting MOS transistor 17 are activated, thereby storing the outputs of the pixels 1 obtained immediately after the pixels 1 have been reset to the capacitor 10. It is now assumed that the output voltage after resetting the pixels 1 is indicated by VRS+NS. Before resetting the pixels 1 to (VRS+NS) again, the terminal 13 is switched on so that the vertical output lines 6 can be reset to VRS, which is the voltage of the reset voltage terminal 9, via the resetting MOS transistor 8.
After switching off the terminal 13, the terminals 14 and 18 are caused to be at a high level, and the pixels 1 are reset to the voltage (VRS+NS) again, which is the same voltage as the capacitor 10, via the MOS transistors 5 and 11.
The charge-storing operation and the charge-reading operation are as follows. The photoelectrically converted charge is stored in the photodiode 2 and the gate of the amplifying MOS transistor 3. After a predetermined period, a signal from the vertical shift register 24 is supplied via the vertical shift register line 26 to the MOS transistors 4 corresponding to the selected line. The terminals 15 and 16 are then caused to be at a high level, and the voltages of the photoelectrically converting pixels 1 are inverted and amplified by using the load current MOS transistors 7 and the amplifying MOS transistors 3 corresponding to the selected line, thereby reading out the voltages of the pixels 1 to the vertical output lines 6. By causing the horizontal shift register 25 to scan, the MOS transistors 21 are sequentially selected via the horizontal shift register lines 27. Accordingly, the output voltages of the pixels 1 are read out from the signal output terminal 23 via the output line 20 and the preamplifier 22.
When the input voltage and the output voltage of the pixel 1 are indicated by VIN and VO, respectively, and the gain of an inversion amplifier formed by the MOS transistors 3 and 7 is represented by gS, the input/output characteristics of the inversion amplifier are expressed by:
VO=xe2x88x92gSxc2x7VIN+VC
where VC indicates a voltage which is determined by the power supply voltage and the threshold of the MOS transistors 3 and 7. Accordingly, if the signal voltage stored in the pixel 1 is designated by xe2x88x92S, the input voltage VIN is expressed by VRS+NSxe2x88x92S. Thus, the output voltage of the pixel 1 is expressed by the following equation.
VO=xe2x88x92gS(VRS+NSxe2x88x92S)+VC
According to the reset operation, the following equation relating input voltage VRS and output voltage (VRS+NS) is given by:
VRS+NS=xe2x88x92gSxc2x7VRS+VC
Therefore, VO is expressed by the following equation.
VO=xe2x88x92gS(xe2x88x92gSxc2x7VRS+VCxe2x88x92S)+VC=gS2xc2x7VRS+(1xe2x88x92gS)VC+gSxc2x7S
The above voltage VC is changed according to the threshold voltage of the MOS transistors 3 and 7.
Generally, since the parameter of the MOS transistor 3 forming the pixel 1 varies to some extent among the pixels 1, the offset level of the pixel 1, i.e., gS2xc2x7VRS+(1xe2x88x92gS)VC appears as fixed pattern noise. In order to increase the signal-to-noise (S/N) ratio, the fixed pattern noise should be eliminated, and thus, the parameters of the MOS transistors 3 and 7 are determined so that gS is equal to 1.
In the above-described conventional apparatus, however, it is difficult to suppress the fixed pattern noise generated by variations in the gains gS of the inversion amplifiers of the individual pixels 1. That is, even if it is desired that gS is set to be 1, there are variations in the parameters of the individual pixels 1, and the gain gS is varied among the pixels 1. As a result, the fixed pattern noise may appear in different levels according to the pixels 1.
More specifically, if a difference of the gain between the pixels 1 is designated by xcex94gS, the gain gS can be indicated by 1+xcex94gS, and the offset potential of each pixel 1 is represented by (1+xcex94gS)2VRSxe2x88x92xcex94gSxc2x7VC. Accordingly, the fixed pattern noise is generated in the individual pixels 1 in different levels according to the difference of gain xcex94gS.
Additionally, because of a change in the voltage VC according to variations of the power supply voltage and variations of the temperature, the fixed pattern noise itself is changed, thereby failing to obtain a high quality image.
Accordingly, it is an object of the present invention to suppress the fixed pattern noise caused by variations in the gain of the individual pixels and in the threshold.
It is another object of the present invention to obtain a high quality image by eliminating variations in the fixed pattern noise caused by the operating conditions of a solid-state imaging apparatus.
In order to achieve the above objects, according to one aspect of the present invention, there is provided a solid-state imaging apparatus including a photoelectric conversion pixel and a self-compensating voltage supply circuit that supplies a reset voltage to the photoelectric conversion pixel.
According to another aspect of the present invention, there is provided a solid-state imaging apparatus including (1) a photoelectric conversion pixel having a photoelectric conversion device and a first amplifier circuit for amplifying a signal supplied from the photoelectric conversion device and (2) a voltage supply circuit including a second amplifier circuit that supplies a reset voltage at least to the photoelectric conversion pixel. The second amplifier circuit has a circuit structure configured similar to that of the first amplifier circuit.
According to a further aspect of the present invention, there is provided a solid-state imaging apparatus including (1) a photoelectric conversion pixel having a photoelectric conversion device and (2) a voltage supply circuit that supplies a reset voltage used for resetting the photoelectric conversion pixel. The reset voltage is supplied from a node at which a control electrode portion of a transistor and an output portion of the transistor are connected, the transistor being configured similarly to a transistor in the photoelectric conversion pixel.
Further objects, features, and advantages of the present invention will become apparent from the following description of the preferred embodiments with reference to the attached drawings.